Service programmable logic arrays with low tunnel barrier interpoly insulators

ABSTRACT

Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5  and/or a Perovskite oxide tunnel barrier.

RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 09/945,512filed on Aug. 30, 2001 which is incorporated herein by reference.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to the following co-pending, commonlyassigned U.S. patent applications: “DRAM Cells with Repressed MemoryMetal Oxide Tunnel Insulators,” Ser. No. 09/945,395, “Programmable ArrayLogic or Memory Devices with Asymmetrical Tunnel Barriers,” Ser. No.09/943,134, “Dynamic Electrically Alterable Programmable Memory withInsulating Metal Oxide Interpoly Insulators,” Ser. No. 09/945,498, and“Flash Memory with Low Tunnel Barrier Interpoly Insulators,” Ser. No.09/945,507, “SRAM Cells with Repressed Floating Gate Memory, Metal OxideTunnel Interpoly Insulators,” Ser. No. 09/945,554, “Programmable MemoryAddress and Decode Devices with Low Tunnel Barrier InterpolyInsulators,” Ser. No. 09/945,500, which are filed on even date herewithand each of which disclosure is herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuits, and inparticular to in-service programmable logic arrays with low tunnelbarrier interpoly insulators.

BACKGROUND OF THE INVENTION

Logic circuits are an integral part of digital systems, such ascomputers. Essentially, a logic circuit processes a number of inputs toproduce a number of outputs for use by the digital system. The inputsand outputs are generally electronic signals that take on one of two“binary” values, a “high” logic value or a “low” logic value. The logiccircuit manipulates the inputs using binary logic which describes, in amathematical way, a given or desired relationship between the inputs andthe outputs of the logic circuit.

Logic circuits that are tailored to the specific needs of a particularcustomer can be very expensive to fabricate on a commercial basis. Thus,general purpose very large scale integration (VLSI) circuits aredefined. VLSI circuits serve as many logic roles as possible, whichhelps to consolidate desired logic functions. However, random logiccircuits are still required to tie the various elements of a digitalsystem together.

Several schemes are used to implement these random logic circuits. Onesolution is standard logic, such as transistor-transistor logic (TTL).TTL integrated circuits are versatile because they integrate only arelatively small number of commonly used logic functions. The drawbackis that large numbers of TTL integrated circuits are typically requiredfor a specific application. This increases the consumption of power andboard space, and drives up the overall cost of the digital system.

One alternative to standard logic is fully custom logic integratedcircuits. Custom logic circuits are precisely tailored to the needs of aspecific application. This allows the implementation of specific circuitarchitectures that dramatically reduces the number of parts required fora system. However, custom logic devices require significantly greaterengineering time and effort, which increases the cost to develop thesecircuits and may also delay the production of the end system.

A less expensive alternative to custom logic is the “programmable logicarray.” Programmable logic arrays take advantage of the fact thatcomplex combinational logic functions can be reduced and simplified intovarious standard forms. For example, logical functions can bemanipulated and reduced down to traditional Sum of Products (SOP) form.In SOP form, a logical function uses just two types of logic functionsthat are implemented sequentially. This is referred to as two-levellogic and can be implemented with various conventional logic functions,e.g., AND-OR, NAND-NAND, NOR-NOR.

One benefit of the programmable logic array is that it provides aregular, systematic approach to the design of random, combinationallogic circuits. A multitude of logical functions can be created from acommon building block, e.g., an array of transistors. The logic array iscustomized or “programmed” by creating a specific metallization patternto interconnect the various transistors in the array to implement thedesired function.

Programmable logic arrays are fabricated using photolithographictechniques that allow semiconductor and other materials to bemanipulated to form integrated circuits as is known in the art. Thesephotolithographic techniques essentially use light that is focusedthrough lenses and masks to define patterns in the materials withmicroscopic dimensions. The equipment and techniques that are used toimplement this photolithography provide a limit for the size of thecircuits that can be formed with the materials. Essentially, at somepoint, the lithography cannot create a fine enough image with sufficientclarity to decrease the size of the elements of the circuit. In otherwords, there is a minimum dimension that can be achieved throughconventional photolithography. This minimum dimension is referred to asthe “critical dimension” (CD) or minimum “feature size” (F) of thephotolithographic process. The minimum feature size imposes oneconstraint on the size of the components of a programmable logic array.In order to keep up with the demands for larger programmable logicarrays, designers search for ways to reduce the size of the componentsof the array.

As the density requirements become higher and higher in logic andmemories it becomes more and more crucial to minimize device area. Theprogrammable logic array (PLA) circuit in the NOR-NOR configuration isone example of an architecture for implementing logic circuits.

Flash memory cells are one possible solution for high density memoryrequirements. Flash memories include a single transistor, and with highdensities would have the capability of replacing hard disk drive datastorage in computer systems. This would result in delicate mechanicalsystems being replaced by rugged, small and durable solid-state memorypackages, and constitute a significant advantage in computer systems.What is required then is a flash memory with the highest possibledensity or smallest possible cell area.

Flash memories have become widely accepted in a variety of applicationsranging from personal computers, to digital cameras and wireless phones.Both INTEL and AMD have separately each produced about one billionintegrated circuit chips in this technology.

The original EEPROM or EARPROM and flash memory devices described byToshiba in 1984 used the interplay dielectric insulator for erase. (Seegenerally, F. Masuoka et al., “A new flash EEPROM cell using triplepolysilicon technology,” IEEE Int. Electron Devices Meeting, SanFrancisco, pp. 464-67, 1984; F. Masuoka et al., “256K flash EEPROM usingtriple polysilicon technology,” IEEE Solid-State Circuits Conf.,Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxideand silicon nitride were tried. (See generally, S. Mori et al.,“reliable CVD inter-poly dialectics for advanced E&EEPROM,” Symp. OnVLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough topsurface of the polysilicon floating gate resulted in, poor qualityinterpoly oxides, sharp points, localized high electric fields,premature breakdown and reliability problems.

Widespread use of flash memories did not occur until the introduction ofthe ETOX cell by INTEL in 1988. (See generally, U.S. Pat. No. 4,780,424,“Process for fabricating electrically alterable floating gate memorydevices,” 25 Oct. 1988; B. Dipert and L. Hebert, “Flash memory goesmainstream,” IEEE Spectrum, pp. 48-51, October, 1993; R. D. Pashley andS. K. Lai, “Flash memories, the best of two worlds,” IEEE Spectrum, pp.30-33, December 1989). This extremely simple cell and device structureresulted in high densities, high yield in production and low cost. Thisenabled the widespread use and application of flash memories anywhere anon-volatile memory function is required. However, in order to enable areasonable write speed the ETOX cell uses channel hot electroninjection, the erase operation which can be slower is achieved byFowler-Nordhiem tunneling from the floating gate to the source. Thelarge barriers to electron tunneling or hot electron injection presentedby the silicon oxide-silicon interface, 3.2 eV, result in slow write anderase speeds even at very high electric fields. The combination of veryhigh electric fields and damage by hot electron collisions in the oxideresult in a number of operational problems like soft erase error,reliability problems of premature oxide breakdown and a limited numberof cycles of write and erase.

Other approaches to resolve the above described problems include; theuse of different floating gate materials, e.g. SiC, SiOC, GaN, andGaAIN, which exhibit a lower work function (see FIG. 1A), the use ofstructured surfaces which increase the localized electric fields (seeFIG. 1B), and amorphous SiC gate insulators with larger electronaffinity, χ, to increase the tunneling probability and reduce erase time(see FIG. 1C).

One example of the use of different floating gate (FIG. 1A) materials isprovided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled “FLASH MEMORYWITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE.”Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes,entitled “FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATINGGATE.” Still further examples of this approach are provided in pendingapplications by L. Forbes and K. Ahn, entitled “DYNAMIC RANDOM ACCESSMEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOWELECTRON AFFINITY GaN OR GaAIN FLOATING GATE,” Ser. No. 08/908098, and“VARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICONCMOS MEMORIES AND IMAGING DEVICES,” Ser. No. 08/903452.

An example of the use of the structured surface approach (FIG. 1B) isprovided in U.S. Pat. no. 5,981,350 by J. Geusic, L. Forbes, and K. Y.Ahn, entitled “DRAM CELLS WITH A STRUCTURE SURFACE USING A SELFSTRUCTURED MASK.” Another example is provided in U.S. Pat. No. 6,025,627by L. Forbes and J. Geusic, entitled “ATOMIC LAYER EXPITAXY GATEINSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES.”

Finally, an example of the use of amorphous SiC gate insulators (FIG.1C) is provided in U.S. patent application Ser. No. 08/903453 by L.Forbes and K. Ahn, entitled “GATE INSULATOR FOR SILICON INTEGRATEDCIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON.”

Additionally, graded composition insulators to increase the tunnelingprobability and reduce erase time have been described by the sameinventors. (See, L. Forbes and J. M. Eldridge, “GRADED COMPOSITION GATEINSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES,”application Ser. No. 09/945,514.

However, all of these approaches relate to increasing tunneling betweenthe floating gate and the substrate such as is employed in aconventional ETOX device and do not involve tunneling between thecontrol gate and floating gate through and inter-poly dielectric.

Therefore, there is a need in the art to provide improved in serviceprogrammable logic arrays. The in-service programmable logic arraysshould provide improved flash memory densities while avoiding the largebarriers to electron tunneling or hot electron injection presented bythe silicon oxide-silicon interface, 3.2 eV, which result in slow writeand erase speeds even at very high electric fields. There is also a needto avoid the combination of very high electric fields and damage by hotelectron collisions in the which oxide result in a number of operationalproblems like soft erase error, reliability problems of premature oxidebreakdown and a limited number of cycles of write and erase. Further,when using an interpoly dielectric insulator erase approach, the abovementioned problems of having a rough top surface on the polysiliconfloating gate which results in, poor quality interpoly oxides, sharppoints, localized high electric fields, premature breakdown andreliability problems must be avoided.

SUMMARY OF THE INVENTION

The above mentioned problems with in service programmable logic arraysand other problems are addressed by the present invention and will beunderstood by reading and studying the following specification. Systemsand methods are provided for in service programmable logic arrays usinglogic cells, or non-volatile memory cells with metal oxide and/or lowtunnel barrier interpoly insulators.

In one embodiment of the present invention, in service programmablelogic arrays with ultra thin vertical body transistors are provided. Thein-service programmable logic array includes a first logic plane thatreceives a number of input signals. The first logic plane has aplurality of logic cells arranged in rows and columns that areinterconnected to provide a number of logical outputs. A second logicplane has a number of logic cells arranged in rows and columns thatreceive the outputs of the first logic plane and that are interconnectedto produce a number of logical outputs such that the in serviceprogrammable logic array implements a logical function. Each of thelogic cells includes includes a first source/drain region and a secondsource/drain region separated by a channel region in a substrate. Afloating gate opposing the channel region and is separated therefrom bya gate oxide. A control gate opposes the floating gate. The control gateis separated from the floating gate by a low tunnel barrier intergateinsulator. The low tunnel barrier intergate insulator includes a metaloxide insulator selected from the group consisting of PbO, Al₂O₃, Ta₂O₅,TiO₂, ZrO₂, and Nb₂O₅. The floating gate includes a polysilicon floatinggate having a metal layer formed thereon in contact with the low tunnelbarrier intergate insulator. And, the control gate includes apolysilicon control gate having a metal layer formed thereon in contactwith the low tunnel barrier intergate insulator.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C illustrate a number of previous methods for reducingtunneling barriers in Flash memory.

FIG. 2 illustrates one embodiment of a floating gate transistor, ornon-volatile memory cell, according to the teachings of the presentinvention.

FIG. 3 illustrates another embodiment of a floating gate transistor, ornon-volatile memory cell, according to the teachings of the presentinvention.

FIG. 4 is a perspective view illustrating an array of silicon pillarsformed on a substrate as used in one embodiment according to theteachings of the present invention.

FIGS. 5A-5E are cross sectional views taken along cut line 5—5 from FIG.4 illustrating a number of floating gate and control gate configurationswhich are included in the scope of the present invention.

FIGS. 6A-6C illustrate a number of address coincidence schemes can beused together with the present invention.

FIG. 7A is an energy band diagram illustrating the band structure atvacuum level with the low tunnel barrier interpoly insulator accordingto the teachings of the present invention.

FIG. 7B is an energy band diagram illustrating the band structure duringan erase operation of electrons from the floating gate to the controlgate across the low tunnel barrier interpoly insulator according to theteachings of the present invention.

FIG. 7C is a graph plotting tunneling currents versus the appliedelectric fields (reciprocal applied electric field shown) for an numberof barrier heights.

FIG. 8 is a schematic diagram illustrating a conventional NOR-NORprogrammable logic array.

FIG. 9 is a schematic diagram illustrating generally an architecture ofone embodiment of a novel in-service programmable logic array (PLA) withfloating gate transistors, or logic cells, according to the teachings ofthe present invention.

FIG. 10 is a simplified block diagram of a high-level organization of anelectronic system according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. The embodiments are intended to describeaspects of the invention in sufficient detail to enable those skilled inthe art to practice the invention. Other embodiments may be utilized andchanges may be made without departing from the scope of the presentinvention. In the following description, the terms wafer and substrateare interchangeably used to refer generally to any structure on whichintegrated circuits are formed, and also to such structures duringvarious stages of integrated circuit fabrication. Both terms includedoped and undoped semiconductors, epitaxial layers of a semiconductor ona supporting semiconductor or insulating material, combinations of suchlayers, as well as other such structures that are known in the art. Thefollowing detailed description is not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizonal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

The present invention, describes the use of metal oxide inter-polydielectric insulators between the control gate and the floating gate. Anexample is shown in FIG. 2 for a planar structure, or horizontalnon-volatile memory cell. According to the teachings of the presentinvention. The use of metal oxide films for this purpose offer a numberof advantages including:

(i) Flexibility in selecting a range of smooth metal film surfaces andcompositions that can be oxidized to form tunnel barrier insulators.

(ii) Employing simple “low temperature oxidation” to produce oxide filmsof highly controlled thickness, composition, purity and uniformity.

(iii) Avoiding inadvertent inter-diffusion of the metal and silicon aswell as silicide formation since the oxidation can be carried out atsuch low temperatures.

(iv) Using metal oxides that provide desirably lower tunnel barriers,relative to barriers currently used such as SiO₂.

(v) Providing a wide range of higher dielectric constant oxide filmswith improved capacitance characteristics.

(vi) Providing a unique ability to precisely tailor tunnel oxide barrierproperties for various device designs and applications.

(vii) Permitting the use of thicker tunnel barriers, if needed, toenhance device performance and its control along with yield andreliability.

(viii) Developing layered oxide tunnel barriers by oxidizing layeredmetal film compositions in order, for example, to enhance device yieldsand reliability more typical of single insulating layers.

(ix) Eliminating soft erase errors caused by the current technique oftunnel erase from floating gate to the source.

FIG. 2 illustrates one embodiment of a floating gate transistor, ornon-volatile memory cell 200, according to the teachings of the presentinvention. As shown in FIG. 2, the non-volatile memory cell 200 includesa first source/drain region 201 and a second source/drain region 203separated by a channel region 205 in a substrate 206. A floating gate209 opposes the channel region 205 and is separated therefrom by a gateoxide 211. A control gate 213 opposes the floating gate 209. Accordingto the teachings of the present invention, the control gate 213 isseparated from the floating gate 209 by a low tunnel barrier intergateinsulator 215.

In one embodiment of the present invention, low tunnel barrier intergateinsulator 215 includes a metal oxide insulator selected from the groupconsisting of lead oxide (PbO) and aluminum oxide (Al₂O₃). In analternative embodiment of the present invention, the low tunnel barrierintergate insulator 215 includes a transition metal oxide and thetransition metal oxide is selected from the group consisting of Ta₂O₅,TiO₂, ZrO₂, and Nb₂O₅. In still another alternative embodiment of thepresent invention, the low tunnel barrier intergate insulator 215includes a Perovskite oxide tunnel barrier.

According to the teachings of the present invention, the floating gate209 includes a polysilicon floating gate 209 having a metal layer 216formed thereon in contact with the low tunnel barrier intergateinsulator 215. Likewise, the control gate 213 includes a polysiliconcontrol gate 213 having a metal layer 217 formed thereon in contact withthe low tunnel barrier intergate insulator 215. In this invention, themetal layers, 216 and 217, are formed of the same metal material used toform the metal oxide interpoly insulator 215.

FIG. 3 illustrates another embodiment of a floating gate transistor, ornon-volatile memory cell 300, according to the teachings of the presentinvention. As shown in the embodiment of FIG. 3, the non-volatile memorycell 300 includes a vertical non volatile memory cell 300. In thisembodiment, the non-volatile memory cell 300 has a first source/drainregion 301 formed on a substrate 306. A body region 307 including achannel region 305 is formed on the first source/drain region 301. Asecond source/drain region 303 is formed on the body region 307. Afloating gate 309 opposes the channel region 305 and is separatedtherefrom by a gate oxide 311. A control gate 313 opposes the floatinggate 309. According to the teachings of the present invention, thecontrol gate 313 is separated from the floating gate 309 by a low tunnelbarrier intergate insulator 315.

According to the teachings of the present invention, the low tunnelbarrier intergate insulator 315 includes a metal oxide insulator 315selected from the group consisting of PbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, andNb₂O₅. In still another alternative embodiment of the present invention,the low tunnel barrier intergate insulator 315 includes a Perovskiteoxide tunnel barrier. The floating gate 309 includes a polysiliconfloating gate 309 having a metal layer 316 formed thereon in contactwith the low tunnel barrier intergate insulator 315. The control gate313 includes a polysilicon control gate 313 having a metal layer 317formed thereon in contact with, the low tunnel barrier intergateinsulator 315.

As shown in FIG. 3, the floating gate 309 includes a vertical floatinggate 309 formed alongside of the body region 307. In the embodimentshown in FIG. 3, the control gate 313 includes a vertical control gate313 formed alongside of the vertical floating gate 309.

As will be explained in more detail below, the floating gate 309 andcontrol gate 313 orientation shown in FIG. 3 is just one embodiment fora vertical non volatile memory cell 300, according to the teachings ofthe present invention. In other embodiments, explained below, thefloating gate includes a horizontally oriented floating gate formedalongside of the body region. In this alternative embodiment, thecontrol gate includes a horizontally oriented control gate formed abovethe horizontally oriented floating gate.

FIG. 4 is a perspective view illustrating an array of silicon pillars400-1, 400-2, 400-3, . . . , 400-N, formed on a substrate 406 as used inone embodiment according to the teachings of the present invention. Aswill be understood by one of ordinary skill in the art upon reading thisdisclosure, the substrates can be (i) conventional p-type bulk siliconor p-type epitaxial layers on p+wafers, (ii) silicon on insulator formedby conventional SIMOX, wafer bonding and etch back or silicon onsapphire, or (iii) small islands of silicon on insulator utilizingtechniques.

As shown in FIG. 4, each pillar in the array of silicon pillars 400-1,400-2, 400-3, . . . , 400-N, includes a first source/drain region 401and a second source/drain region 403. The first and the secondsource/drain regions, 401 and 403, are separated by a body region 407including channel regions 405. As shown in FIG. 4, a number of trenches430 separate adjacent pillars in the array of silicon pillars 400-1,400-2, 400-3, . . . , 400-N. Trenches 430 are referenced in connectionwith the discussion which follows in connection with FIGS. 5A-5E.

FIGS. 5A-5E are cross sectional views taken along cut line 5—5 from FIG.4. As mentioned above in connection with FIG. 3, a number of floatinggate and control gate configurations are included in the presentinvention. FIG. 5A illustrates one such embodiment of the presentinvention. FIG. 5A illustrates a first source/drain region 501 andsecond source/drain region 503 for a non-volatile memory cell 500 formedaccording to the teachings of the present invention. As shown in FIG. 5,the first and second source/drain regions, 501 and 503, are contained ina pillar of semiconductor material, and separated by a body region 507including channel regions 505. As shown in the embodiments of FIGS.5A-5E, the first source/drain region 501 is integrally connected to aburied sourceline 525. As one or ordinary skill in the art willunderstand upon reading this disclosure the buried sourceline 525 is beformed of semiconductor material which has the same doping type as thefirst source/drain region 501. In one embodiment, the sourceline 525 isformed of semiconductor material of the same doping as the firstsource/drain region 501, but is more heavily doped than the firstsource/drain region 501.

As shown in the embodiment of FIG. 5A, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In this embodiment, a single control gate 513 is shared by the pair offloating gates 509-1 and 509-2 on opposing sides of the trench 530. Asone of ordinary skill in the art will understand upon reading thisdisclosure, the shared single control gate 513 can include an integrallyformed control gate line. As shown in FIG. 5A, such an integrally formedcontrol gate line 513 can be one of a plurality of control gate lineswhich are each independently formed in the trench, such as trench 530,below the top surface of the pillars 500-1 and 500-2 and between thepair of floating gates 509-1 and 509-2. In one embodiment, according tothe teachings of the present invention, each floating gate, e.g. 509-1and 509-2, includes a vertically oriented floating gate having avertical length of less than 100 nanometers.

As shown in the embodiment of FIG. 5B, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In the embodiment of FIG. 5B, a plurality of control gate lines areagain formed in trenches, e.g. trench 530, below the top surface of thepillars, 500-1 and 500-2, and between the pair of floating gates 509-1and 509-2. However, in this embodiment, each trench, e.g. 530, houses apair of control gate lines, shown as 513-1 and 513-2. Each one of thepair of control gate lines 513-1 and 513-2 adresses the floating gates,509-1 and 509-2 respectively, on opposing sides of the trench 530. Inthis embodiment, the pair of control gate lines, or control gates 513-1and 513-2 are separated by an insulator layer.

As shown in the embodiment of FIG. 5C, a pair of floating gates 509-1and 509-2 are again formed in each trench 530 between adjacent pillarswhich form memory cells 500-1 and 500-2. Each one of the pair offloating gates, 509-1 and 509-2, respectively opposes the body regions507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides ofthe trench 530.

In the embodiment of FIG. 5C, the plurality of control gate lines aredisposed vertically above the floating gates. That is, in oneembodiment, the control gate lines are located above the pair offloating gates 509-1 and 509-2 and not fully beneath the top surface ofthe pillars 500-1 and 500-2. In the embodiment of FIG. 5C, each pair offloating gates, e.g. 509-1 and 509-2, in a given trench shares a singlecontrol gate line, or control gate 513.

As shown in the embodiment of FIG. 5D, a pair of floating gates 509-1and 509-2 are formed in each trench 530 between adjacent pillars whichform memory cells 500-1 and 500-2. Each one of the pair of floatinggates, 509-1 and 509-2, respectively opposes the body regions 507-1 and507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of thetrench 530.

In the embodiment of FIG. 5D, the plurality of control gate lines aredisposed vertically above the floating gates. That is, in oneembodiment, the control gate lines are located above the pair offloating gates 509-1 and 509-2 and not fully beneath the top surface ofthe pillars 500-1 and 500-2. However, in the embodiment of FIG. 5D, eachone of the pair of floating gates, e.g. 509-1 and 509-2, is addressed byan independent one of the plurality of control lines or control gates,shown in FIG. 5D as 513-1 and 513-2.

As shown in the embodiment of FIG. 5E, a single floating gate 509 isformed in each trench 530 between adjacent pillars which form memorycells 500-1 and 500-2. According to the teachings of the presentinvention, the single floating gate 509 can be either a verticallyoriented floating gate 509 or a horizontally oriented floating gate 509formed by conventional processing techniques, or can be a horizontallyoriented floating gate 509 formed by a replacement gate technique. Inone embodiment of the present invention, the floating gate 509 has avertical length facing the body region 505 of less than 100 nm. Inanother embodiment, the floating gate 509 has a vertical length facingthe body region 505 of less than 50 nm. In one embodiment, as shown inFIG. 5E, the floating gate 509 is shared, respectively, with the bodyregions 507-1 and 507-2, including channel regions 505-1 and 505-2, inadjacent pillars 500-1 and 500-2 located on opposing sides of the trench530. And, as shown in FIG. 5E, the control gate includes a singlehorizontally oriented control gate line, or control gate 513 formedabove the horizontally oriented floating gate 509.

As one of ordinary skill in the art will understand upon reading thisdisclosure, in each of the embodiments described above in connectionwith FIGS. 5A-5E the floating gates 509 are separated from the controlgate lines, or control gates 513 with a low tunnel barrier intergateinsulator in accordance with the descriptions given above in connectionwith FIG. 3. The modifications here are to use tunneling through theinterpoly dielectric to realize flash memory devices. The verticaldevices include an extra flexibility in that the capacitors, e.g. gateoxide and intergate insulator, are easily fabricated with differentareas. This readily allows the use of very high dielectric constantinter-poly dielectric insulators with lower tunneling barriers.

FIGS. 6A-6C illustrate that a number of address coincidence schemes canbe used together with the present invention. FIG. 6A illustrates a NORflash memory array 610 having a number of non-volatile memory cells600-1, 600-2, 600-3, using a coincidence address array scheme. Forpurposes of illustration, FIG. 6A shows a sourceline 625 coupled to afirst source/drain region 601 in each of the number of non-volatilememory cells 600-1, 600-2, 600-3. The sourceline is shown oriented in afirst selected direction in the flash memory array 610. In FIG. 6A, anumber of control gate lines 630 are shown oriented in a second selecteddirection in the flash memory array 610. As shown in FIG. 6A, the numberof control gate lines 630 are coupled to, or integrally formed with thecontrol gates 613 for the number of non-volatile memory cells 600-1,600-2, 600-3. As shown in FIG. 6A, the second selected direction isorthogonal to the first selected direction. Finally, FIG. 6A shows anumber of bitlines 635 oriented in a third selected direction in theflash memory array 610. As shown in FIG. 6A, the number of bitlines arecoupled to the second source/drain regions in the number of non-volatilememory cells 600-1, 600-2, 600-3. In the embodiment shown in FIG. 6A thethird selected direction is parallel to the second selected directionand the number of control gate lines 630 serve as address lines. Also,as shown in FIG. 6A, the flash memory array 610 includes a number ofbackgate or substrate/well bias address lines 640 coupled to thesubstrate.

Using FIG. 6A as a reference point, FIGS. 6B-6C illustrate of top viewfor three different coincidence address scheme layouts suitable for usewith the present invention. First, FIG. 6B provides the top view layoutof the coincidence address scheme described in connection with FIG. 6A.This is, FIG. 6B illustrates a number of sourcelines 625 oriented in afirst selected direction, a number of control gate lines 630 oriented ina second selected direction, and a number of bitlines 635 oriented in athird selected direction for the flash memory array 600. In theembodiment of FIG. 6B, the first selected direction and the thirdselected direction are parallel to one another and orthogonal to thesecond selected direction. In this embodiment, the number of controlgate lines 630 serve as address lines. According to the teachings of thepresent invention the output lines, e.g. bitlines 635 must beperpendicular to the address lines, e.g. in this embodiment control gatelines 630.

FIG. 6C provides the top view layout of yet another coincidence addressscheme according to the teachings of the present invention. This is,FIG. 6C illustrates a number of sourcelines 625 oriented in a firstselected direction, a number of control gate lines 630 oriented in asecond selected direction, and a number of bitlines 635 oriented in athird selected direction for the flash memory array 600. In theembodiment of FIG. 6C, the first selected direction and the secondselected direction are parallel to one another and orthogonal to thethird selected direction. In this embodiment, the number of bitlines 635serve as address lines. In an alternative embodiment, the sourcelines625 can include a uniform ground plane as the same will be known andunderstood by one of ordinary skill in the art.

As will be apparent to one of ordinary skill in the art upon readingthis disclosure, and as will be described in more detail below, writecan still be achieved by hot electron injection and/or, according to theteachings of the present invention, tunneling from the control gate.According to the teachings of the present invention, block erase isaccomplished by driving the control gates with a relatively largepositive voltage and tunneling from the metal on top of the floatinggate to the metal on the bottom of the control gate.

FIG. 7A is an energy band diagram illustrating the band structure atvacuum level with the low tunnel barrier interpoly insulator accordingto the teachings of the present invention. FIG. 7A is useful inillustrating the reduced tunnel barrier off of the floating gate to thecontrol gate and for illustrating the respective capacitances of thestructure according to the teachings of the present invention.

FIG. 7A shows the band structure of the silicon substrate, e.g. channelregion 701, silicon dioxide gate insulator, e.g. gate oxide 703,polysilicon floating gate 705, the low tunnel barrier interpolydielectric 707, between metal plates 709 and 711, and then thepolysilicon control gate 713, according to the teachings of the presentinvention.

The design considerations involved are determined by the dielectricconstant, thickness and tunneling barrier height of the interpolydielectric insulator 707 relative to that of the silicon dioxide gateinsulator, e.g. gate oxide 703. The tunneling probability through theinterpoly dielectric 707 is an exponential function of both the barrierheight and the electric field across this dielectric.

FIG. 7B is an energy band diagram illustrating the band structure duringan erase operation of electrons from the floating gate 705 to thecontrol gate 713 across the low tunnel barrier interpoly insulator 707according to the teachings of the present invention. FIG. 7B issimilarly useful in illustrating the reduced tunnel barrier off of thefloating gate to the control gate and for illustrating the respectivecapacitances of the structure according to the teachings of the presentinvention.

As shown in FIG. 7B, the electric field is determined by the totalvoltage difference across the structure, the ratio of the capacitances(see FIG. 7A), and the thickness of the interpoly dielectric 707. Thevoltage across the interpoly dielectric 707 will be, ΔV2=V C1/(C1+C2),where V is the total applied voltage. The capacitances, C, of thestructures depends on the dielectric constant, ∈_(r), or thepermittivity of free space, e_(o), and the thickness of the insulatinglayers, t, and area, A, such that C=∈_(r)∈_(o)A/t, Farads/cm², where∈_(r) represents the low frequency dielectric constant. The electricfield across the interpoly dielectric insulator 707, having capacitance,C2, will then be E2=ΔV2/t2, where t2 is the thickness of this layer.

The tunneling current in erasing charge from the floating gate 705 bytunneling to the control gate 713 will then be as shown in FIG. 7B givenby an equation of the form:J=B exp(−Eo/E)$J = {{\frac{q^{2}E^{2}}{4\quad\pi\quad h\quad\Phi}e^{{- E_{O}}/E}\quad E_{O}} = {\frac{8\pi}{3}\quad\frac{\sqrt{2m\overset{*}{q}}\Phi\frac{3}{2}}{h}}}$where E is the electric field across the interpoly dielectric insulator707 and Eo depends on the barrier height. Aluminum oxide has a currentdensity of 1 A/cm² at a field of about E=1V/20 A=5×10⁺⁶ V/cm. Siliconoxide transistor gate insulators have a current density of 1 A/cm² at afield of about E=2.3V/23 A=1×10⁺⁷ V/cm.

The lower electric field in the aluminum oxide interpoly insulator 707for the same current density reflects the lower tunneling barrier ofless than 2 eV, shown in FIG. 7B, as opposed to the 3.2 eV tunnelingbarrier of silicon oxide 703, also illustrated in FIG. 7B.

FIG. 7C is a graph plotting tunneling currents versus the appliedelectric fields (reciprocal applied electric field shown) for an numberof barrier heights. FIG. 7C illustrates the dependence of the tunnelingcurrents on electric field (reciprocal applied electric field) andbarrier height. The fraction of voltage across the interpoly orintergate insulator, ΔV2, can be increased by making the area of theintergate capacitor, C2, (e.g. intergate insulator 707) smaller than thearea of the transistor gate capacitor, C1 (e.g. gate oxide 703). Thiswould be required with high dielectric constant intergate dielectricinsulators 707 and is easily realized with the vertical floating gatestructures described above in connection with FIGS. 3, and 5A-5E.

Methods of Formation

Several examples are outlined below in order to illustrate how adiversity of such metal oxide tunnel barriers can be formed, accordingto the teachings of the present invention. Processing details andprecise pathways taken which are not expressly set forth below will beobvious to one of ordinary skill in the art upon reading thisdisclosure. Firstly, although not included in the details below, it isimportant also to take into account the following processing factors inconnection with the present invention:

(i) The poly-Si layer is to be formed with emphasis on obtaining asurface that is very smooth and morphologically stable at subsequentdevice processing temperatures which will exceed that used to grow Metaloxide.

(ii) The native SiO_(x) oxide on the poly-Si surface must be removed(e.g., by sputter cleaning in an inert gas plasma in situ) just prior todepositing the metal film. The electrical characteristics of theresultant Poly-Si/Metal/Metal oxide/Metal/Poly-Si structure will bebetter defined and reproducible than that of a Poly-Si/NativeSiO_(x)/Metal/Metal oxide/Poly-Si structure.

(iii) The oxide growth rate and limiting thickness will increase withoxidation temperature and oxygen pressure. The oxidation kinetics of ametal may, in some cases, depend on the crystallographic orientations ofthe very small grains of metal which comprise the metal film. If sucheffects are significant, the metal deposition process can be modified inorder to increase its preferred orientation and subsequent oxidethickness and tunneling uniformity. To this end, use can be made of thefact that metal films strongly prefer to grow during their depositionshaving their lowest free energy planes parallel to the film surface.This preference varies with the crystal structure of the metal. Forexample, fcc metals prefer to form {111} surface plans. Metalorientation effects, if present, would be larger when only a limitedfraction of the metal will be oxidized and unimportant when all or mostof the metal is oxidized.

(iv) Modifications in the structure shown in FIG. 2 may be introduced inorder to compensate for certain properties in some metal/oxide/metallayers. Such changes are reasonable since a wide range of metals, alloysand oxides with quite different physical and chemical properties can beused to form these tunnel junctions.

EXAMPLE I Formation of PbO Tunnel Barriers

This oxide barrier has been studied in detail using Pb/PbO/Pbstructures. The oxide itself can be grown very controllably on depositedlead films using either thermal oxidation or rf sputter etching in anoxygen plasma. It will be seen that there are a number of possiblevariations on this structure. Starting with a clean poly-Si substrate,one processing sequence using thermal oxidation involves:

(i) Depositing a clean lead film on the poly-Si floating gate at ˜25 to75 C. in a clean vacuum system having a base pressure of ˜10⁻⁸ Torr orlower. The Pb film will be very thin with a thickness within 1 or 2 A ofits target value.

(ii) Lead and other metal films can be deposited by various meansincluding physical sputtering and/or from a Knudsen evaporation cell.The sputtering process also offers the ability to produce smoother filmsby increasing the re-sputtering-to-deposition ratio since re-sputteringpreferentially reduces geometric high points of the film.

(iii) Using a “low temperature oxidation process” to grow an oxide filmof self-limited thickness. In this case, oxygen gas is introduced at thedesired pressure in order to oxidize the lead in situ without anintervening exposure to ambient air. For a fixed oxygen pressure andtemperature, the PbO thickness increases with log(time). Its thicknesscan be controlled via time or other parameters to within 0.10 A, asdetermined via in situ ellipsometric or ex situ measurements ofJosephson tunneling currents. This control is demonstrated by the verylimited statistical scatter of the current PbO thickness data shown inthe insert of FIG. 3. This remarkable degree of control over tunnelcurrent is due to the excellent control over PbO thickness that can beachieved by “low temperature oxidation.” For example, increasing theoxidation time from 100 to 1,000 minutes at an oxygen pressure of 750Torr at 25 C. only raises the PbO thickness by 3 A (e.g., from ˜21 to 24A. Accordingly, controlling the oxidation time to within 1 out of anominal 100 minute total oxidation time provides a thickness that iswithin 0.1 A of 21 A. The PbO has a highly stoichiometric compositionthroughout its thickness, as evidenced from ellipsometry and the factthat the tunnel barrier heights are identical for Pb/PbO/Pb structures.

(iv) Re-evacuate the system and deposit the top lead electrode. Thisproduces a tunnel structure having virtually identical tunnel barriersat both Pb/O interfaces.

(v) The temperature used to subsequently deposit the Poly-Si controlgate must be held below the melting temperature (327 C.) of lead. ThePbO itself is stable (up to ˜500 C. or higher) and thus introduces notemperature constraint on subsequent processes. One may optionallyoxidize the lead film to completion, thereby circumventing the lowmelting temperature of metallic lead. In this case, one would form aPoly-Si/PbO/Poly-Si tunnel structure having an altered tunnel barrierfor charge injection. Yet another variation out of several wouldinvolve: oxidizing the lead film to completion; replacing the top leadelectrode with a higher melting metal such as Al; and, then adding thepoly-Si control layer. This junction would have asymmetrical tunnelingbehavior due to the difference in barrier heights between the Pb/PbO andPbO/Al electrodes.

EXAMPLE II Formation of Al₂O₃ Tunnel Barriers

A number of studies have dealt with electron tunneling in Al/Al₂O₃/Alstructures where the oxide was grown by “low temperature oxidation” ineither molecular or plasma oxygen. Before sketching out a processingsequence for these tunnel barriers, note:

(i) Capacitance and tunnel measurements indicate that the Al₂O₃thickness increases with the log (oxidation time), similar to that foundfor PbO/Pb as well as a great many other oxide/metal systems.

(ii) Tunnel currents are asymmetrical in this system with somewhatlarger currents flowing when electrons are injected from Al/Al₂O₃interface developed during oxide growth. This asymmetry is due to aminor change in composition of the growing oxide: there is a smallconcentration of excess metal in the Al₂O₃, the concentration of whichdiminishes as the oxide is grown thicker. The excess Al⁺³ ions produce aspace charge that lowers the tunnel barrier at the inner interface. Theoxide composition at the outer Al₂O₃/Al contact is much morestoichiometric and thus has a higher tunnel barrier. In situellipsometer measurements on the thermal oxidation of Al films depositedand oxidized in situ support this model. In spite of this minorcomplication, Al/Al₂O₃/Al tunnel barriers can be formed that willproduce predictable and highly controllable tunnel currents that can beejected from either electrode. The magnitude of the currents are stillprimarily dominated by Al₂O₃ thickness which can be controlled via theoxidation parametrics.

With this background, we can proceed to outline one process path out ofseveral that can be used to form Al₂O₃ tunnel barriers. Here thealuminum is thermally oxidized although one could use other techniquessuch as plasma oxidation or rf sputtering in an oxygen plasma. For thesake of brevity, some details noted above will not be repeated. Theformation of the Al/Al₂O₃/Al structures will be seen to be simpler thanthat described for the Pb/PbO/Pb junctions owing to the much highermelting point of aluminum, relative to lead.

(i) Sputter deposit aluminum on poly-Si at a temperature of ˜25 to 150C. Due to thermodynamic forces, the micro-crystallites of the f.c.c.aluminum will have a strong and desirable (111) preferred orientation.

(ii) Oxidize the aluminum in situ in molecular oxygen usingtemperatures, pressure and time to obtain the desired Al₂O₃ thickness.As with PbO, the thickness increases with log (time) and can becontrolled via time at a fixed oxygen pressure and temperature to within0.10 Angstroms, when averaged over a large number of aluminum grainsthat are present under the counter-electrode. One can readily change theAl₂O₃ thickness from ˜15 to 35 A by using appropriate oxidationparametrics. The oxide will be amorphous and remain so untiltemperatures in excess of 400 C. are reached. The initiation ofrecrystallization and grain growth can be suppressed, if desired, viathe addition of small amounts of glass forming elements (e.g., Si)without altering the growth kinetics or barrier heights significantly.

(iii) Re-evacuate the system and deposit a second layer of aluminum.

(iv) Deposit the Poly-Si control gate layer using conventionalprocesses.

EXAMPLE III Formation of Single- and Multi-Layer Transition Metal OxideTunnel Barriers.

Single layers of Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅ and similar transition metaloxides can be formed by “low temperature oxidation” of numerousTransition Metal (e.g., TM oxides) films in molecular and plasma oxygenand also by rf sputtering in an oxygen plasma. The thermal oxidationkinetics of these metals have been studied for decades. In essence, suchmetals oxidize via logarithmic kinetics to reach thicknesses of a few toseveral tens of angstroms in the range of 100 to 300 C. Excellent oxidebarriers for Josephson tunnel devices can be formed by rf sputteretching these metals in an oxygen plasma. Such “low temperatureoxidation” approaches differ considerably from MOCVD processes used toproduce these TM oxides. MOCVD films require high temperature oxidationtreatments to remove carbon impurities, improve oxide stoichiometry andproduce recrystallization. Such high temperature treatments also causeunwanted interactions between the oxide and the underlying silicon andthus have necessitated the introduction of interfacial barrier layers.

An approach was developed utilizing “low temperature oxidation” to formduplex layers of TM oxides. Unlike MOCVD films, the oxides are very pureand stoichiometric as formed. They do require at least a brief hightemperature (est. 700 to 800 C. but may be lower) treatment to transformtheir microstructures from amorphous to crystalline and thus increasetheir dielectric constants to the desired values (>20 or so). UnlikeMOCVD oxides, this treatment can be carried out in an inert gasatmosphere, thus lessening the possibility of inadvertently oxidizingthe poly-Si floating gate. While this earlier disclosure was directed atdeveloping methods and procedures for producing high dielectric constantfilms for storage cells for DRAMs, the same teachings can be applied toproducing thinner metal oxide tunnel films for the flash memory devicesdescribed in this disclosure. The dielectric constants of these TMoxides are substantially greater (>25 to 30 or more) than those of PbOand Al₂O₃. Duplex layers of these high dielectric constant oxide filmsare easily fabricated with simple tools and also provide improvement indevice yields and reliability. Each oxide layer will contain some levelof defects but the probability that such defects will overlap isexceedingly small. Effects of such duplex layers were first reported byone J. M. Eldridge of the present authors and are well known topractitioners of the art. It is worth mentioning that highlyreproducible TM oxide tunnel barriers can be grown by rf sputtering inan oxygen ambient. Control over oxide thickness and other properties inthese studies were all the more remarkable in view of the fact that theoxides were typically grown on thick (e.g., 5,000 A) metals such as Nband Ta. In such metal-oxide systems, a range of layers and suboxides canalso form, each having their own properties. In the present disclosure,control over the properties of the various TM oxides will be even bettersince we employ very limited (perhaps 10 to 100 A or so) thicknesses ofmetal and thereby preclude the formation of significant quantities ofunwanted, less controllable sub-oxide films. Thermodynamic forces willdrive the oxide compositions to their most stable, fully oxidized state,e.g., Nb₂O₅, Ta₂O₅, etc. As noted above, it will still be necessary tocrystallize these duplex oxide layers. Such treatments can be done byRTP and will be shorter than those used on MOCVD and sputter-depositedoxides since the stoichiometry and purity of the “low temperatureoxides” need not be adjusted at high temperature.

Fairly detailed descriptions for producing thicker duplex layers of TMoxides have been given in the copending application by J. M. Eldridge,entitled “Thin Dielectric Films for DRAM Storage Capacitors,” patentapplication Ser. No. 09/651,380 filed Aug. 29, 2000, so there is no needto repeat them here. Although perhaps obvious to those skilled in theart, one can sketch out a few useful fabrication guides:

(i) Thinner TM layers will be used in this invention relative to thoseused to form DRAMs. Unlike DRAMs where leakage must be eliminated, theduplex oxides used here must be thin enough to carry very controlledlevels of current flow when subjected to reasonable applied fields andtimes.

(ii) The TM and their oxides are highly refractory and etchable (e.g.,by RIE). Hence they are quite compatible with poly-Si control gateprocesses and other subsequent steps.

(iii) TM silicide formation will not occur during the oxidation step. Itcould take place at a significant rate at the temperatures used todeposit the poly-Si control gate. If so, several solutions can beapplied including:

-   -   (i) Insert certain metals at the TM/poly-Si boundaries that will        prevent inter-diffusion of the TM and the poly-Si.    -   (ii) Completely oxide the TMs. The electrical characteristics of        the resulting poly-Si/TM oxide 1/TM oxide 2/poly-Si structure        will be different in the absence of having TM at the oxide/metal        interfaces.

EXAMPLE IV Formation of Alternate Metal Compound Tunnel Barriers.

Although no applications may be immediately obvious, it is conceivablethat one might want to form a stack of oxide films having quitedifferent properties, for example, a stack comprised of a highdielectric constant (k) oxide/a low k oxide/a high k oxide. “Lowtemperature oxidation” can be used to form numerous variations of suchstructures. While most of this disclosure deals with the formation anduse of stacks of oxide dielectrics, it is also possible to use “lowtemperature oxidation” to form other thin film dielectrics such asnitrides, oxynitrides, etc. that could provide additional functions suchas being altered by monochromatic light, etc. These will not bediscussed further here.

EXAMPLE V Formation of Perovskite Oxide Tunnel Barriers.

Some results have been obtained which demonstrate that at least alimited range of high temperature, super-conducting oxide films can bemade by thermally oxidizing Y—Ba—Cu alloy films. The present inventorshave also disclosed how to employ “low temperature oxidation” and shortthermal treatments in an inert ambient at 700 C. in order to form arange of perovskite oxide films from parent alloy films. The dielectricconstants of crystallized, perovskite oxides can be very large, withvalues in the 100 to 1000 or more range. The basic process is morecomplicated than that needed to oxidize layered films of transitionmetals. (See Example III.) The TM layers would typically be pure metalsalthough they could be alloyed. The TMs are similar metallurgically asare their oxides. In contrast, the parent alloy films that can beconverted to a perovskite oxide are typically comprised of metals havingwidely different chemical reactivities with oxygen and other commongasses. In the Y—Ba—Cu system referenced above, Y and Ba are among themost reactive of metals while the reactivity of Cu approaches (albeitdistantly) those of other noble metals. If the alloy is to be completelyoxidized, then thin film barriers such as Pd, Pt, etc. or theirconductive oxides must be added between the Si and the parent metal filmto serve as: electrical contact layers; diffusion barriers; and,oxidation stops. In such a case, the Schottky barrier heights of variousTM oxides and perovskite oxides in contact with various metals will helpin the design of the tunnel device. In the more likely event that theperovskite parent alloy film will be only partially converted to oxideand then covered with a second layer of the parent alloy (recall thestructure of FIG. 2), then the barrier heights will represent thatdeveloped during oxide growth at the parent perovskite alloy/perovskiteoxide interface. Obviously, such barrier heights cannot be predicted abinitio for such a wide class of materials but will have to be developedas the need arises. This information will have to be developed on asystem-by-system basis.

Methods of Operation

Write Operation

Write can be achieved by the normal channel hot electron injection andgate current through the silicon oxide to the floating gate. This isdone by selecting a particular column by applying a high control gatevoltage and applying relatively large drain voltage as is done withconventional ETOX flash memory devices. However, according to theteachings of the present invention, write can also be accomplished byapplying a positive voltage to the substrate or well select line and alarge negative voltage to the control gates, electrons will tunnel fromthe control gate to the floating gate. The low tunnel barrier willprovide an easy write operation and the selection of the substrate orwell bias will provide selectivity and address only one device.

Erase Operation

According to the teachings of the present invention, erase is achievedby providing a negative voltage to the substrate or well address lineand a large positive voltage to the control gate. This causes electronsto tunnel off of the floating gate on to the control gate. A whole rowcan be erased by addressing all the column lines along that row and ablock can be erased by addressing multiple row back gate orsubstrate/well address lines.

Read Operation

Read is accomplished as in conventional ETOX flash memory devices. Acolumn line is addressed by applying a positive control gate voltage andsensing the current along the data bit or drain row address line.

System Level

FIG. 8 shows a conventional NOR-NOR logic array 800 which isprogrammable at the gate mask level by either fabricating a thin oxidegate transistor, e.g. logic cells 801-1, 801-2, . . . , 801-N and 803-1,803-2, . . . , 803-N, at the intersection of lines in the array or notfabricating a thin oxide gate transistor, e.g. missing thin oxidetransistors, 802-1, 802-2, . . . , 802-N, at such an intersection. Asone of ordinary skill in the art will understand upon reading thisdisclosure, the same technique is conventionally used to form othertypes of logic arrays not shown. As shown in FIG. 8, a number ofdepletion mode NMOS transistors, 816 and 818 respectively, are used asload devices.

The conventional logic array shown in FIG. 8 includes a first logicplane 810 which receives a number of input signals at input lines 812.In this example, no inverters are provided for generating complements ofthe input signals. However, first logic plane 810 can include invertersto produce the complementary signals when needed in a specificapplication.

First logic plane 810 includes a number of thin oxide gate transistors,e.g. transistors 801-1, 801-2, . . . , 801-N. The thin oxide gatetransistors, 801-1, 801-2, . . . , 801-N, are located at theintersection of input lines 812, and interconnect lines 814. In theconventional PLA of FIG. 8, this selective fabrication of thin oxidegate transistor, e.g. transistors 801-1, 801-2, . . . , 801-N, isreferred to as programming since the logical function implemented by theprogrammable logic array is entered into the array by the selectivearrangement of the thin oxide gate transistors, or logic cells, 801-1,801-2, . . . , 801-N, at the intersections of input lines 812, andinterconnect lines 814 in the array.

In this embodiment, each of the interconnect lines 814 acts as a NORgate for the input lines 812 that are connected to the interconnectlines 814 through the thin oxide gate transistors, 801-1, 801-2, . . . ,801-N, of the array. For example, interconnection line 814A acts as aNOR gate for the signals on input lines 812A and 812B. That is,interconnect line 814A is maintained at a high potential unless one ormore of the thin oxide gate transistors, 801-1, 801-2, . . . , 801-N,that are coupled to interconnect line 814A are turned on by a high logiclevel signal on one of the input lines 812. When a control gate addressis activated, through input lines 812, each thin oxide gate transistor,e.g. transistors 801-1, 801-2, . . . , 801-N, conducts which performsthe NOR positive logic circuit function, an inversion of the OR circuitfunction results from inversion of data onto the interconnect lines 814through the thin oxide gate transistors, 801-1, 801-2, . . . , 801-N, ofthe array.

As shown in FIG. 8, a second logic plane 824 is provided which includesa number of thin oxide gate transistor, e.g. transistors 803-1, 803-2, .. . , 803-N. The thin oxide gate transistors, 803-1, 803-2, . . . ,803-N, are located at the intersection of interconnect lines 814, andoutput lines 820. Here again, the logical function of the second logicplane 824 is implemented by the selective arrangement of the thin oxidegate transistors, 803-1, 803-2, . . . , 803-N, at the intersections ofinterconnect lines 814, and output lines 820 in the second logic plane824. The second logic plane 824 is also configured such that the outputlines 820 comprise a logical NOR function of the signals from theinterconnection lines 814 that are coupled to particular output lines820 through the thin oxide gate transistors, 803-1, 803-2, . . . ,803-N, of the second logic plane 824. Thus, in FIG. 8, the incomingsignals on each line are used to drive the gates of transistors in theNOR logic array as the same is known by one of ordinary skill in the artand will be understood by reading this disclosure.

FIG. 9 illustrates an embodiment of a novel in-service programmablelogic array (PLA) formed according to the teachings of the presentinvention. In FIG. 9, PLA 900 implements an illustrative logicalfunction using a two level logic approach. Specifically, PLA 900includes first and second logic planes 910 and 922. In this example, thelogic function is implemented using NOR-NOR logic. As shown in FIG. 9,first and second logic planes 910 and 922 each include an array of,logic cells, non-volatile memory cells, or floating gate drivertransistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . ,902-N respectively, formed according to the teachings of the presentinvention. The floating gate driver transistors, 901-1, 901-2, . . . ,901-N, and 902-1, 902-2, . . . , 902-N, have their first source/drainregions coupled to source lines or a conductive source plane, as shownand described in more detail in connection with FIGS. 2 and 7C. Thesefloating gate driver transistors, 901-1, 901-2, . . . , 901-N, and902-1, 902-2, . . . , 902-N are configured to implement the logicalfunction of FPLA 900. The floating gate driver transistors, 901-1,901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N are shown asn-channel floating gate transistors. However, the invention is not solimited. Also, as shown in FIG. 9, a number of p-channel metal oxidesemiconductor (PMOS) transistors are provided as load devicetransistors, 916 and 924 respectively, having their source regionscoupled to a voltage potential (VDD). These load device transistors, 916and 924 respectively, operate in complement to the floating gate drivertransistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . ,902-N to form load inverters.

It is noted that the configuration of FIG. 9 is provided by way ofexample and not by way of limitation. Specifically, the teachings of thepresent application are not limited to programmable logic arrays in theNOR-NOR approach. Further, the teachings of the present application arenot limited to the specific logical function shown in FIG. 9. Otherlogical functions can be implemented in a programmable logic array, withthe floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and902-1, 902-2, . . . , 902-N and load device transistors, 916 and 924respectively, of the present invention, using any one of the various twolevel logic approaches.

First logic plane 910 receives a number of input signals at input lines912. In this example, no inverters are provided for generatingcomplements of the input signals. However, first logic plane 910 caninclude inverters to produce the complementary signals when needed in aspecific application.

First logic plane 910 includes a number of floating gate drivertransistors, 901-1, 901-2, . . . , 901-N, that form an array such as anarray of non-volatile memory cells, or flash memory cells. The floatinggate driver transistors, 901-1, 901-2, . . . , 901-N, are located at theintersection of input lines 912, and interconnect lines 914. Not all ofthe floating gate driver transistors, 901-1, 901-2, . . . , 901-N, areoperatively conductive in the first logic plane. Rather, the floatinggate driver transistors, 901-1, 901-2, . . . , 901-N, are selectivelyprogrammed, as described in detail below, to respond to the input lines912 and change the potential of the interconnect lines 914 so as toimplement a desired logic function. This selective interconnection isreferred to as programming since the logical function implemented by theprogrammable logic array is entered into the array by the floating gatedriver transistors, 901-1, 901-2, . . . , 901-N, that are used at theintersections of input lines 912, and interconnect lines 914 in thearray.

In this embodiment, each of the interconnect lines 914 acts as a NORgate for the input lines 912 that are connected to the interconnectlines 914 through the floating gate driver transistors, 901-1, 901-2, .. . , 901-N, of the array 900. For example, interconnection line 914Aacts as a NOR gate for the signals on input lines 912A, 912B and 912C.Programmability of the vertical floating gate driver transistors, 901-1,901-2, . . . , 901-N is achieved by charging the vertical floatinggates. When the vertical floating gate is charged, that floating gatedriver transistor, 901-1, 901-2, . . . , 901-N will remain in an offstate until it is reprogrammed. Applying and removing a charge to thevertical floating gates is performed by tunneling charge between thefloating gate and control gates of the floating gate driver transistors,901-1, 901-2, . . . , 901-N through a low tunnel barrier interpoly, orintergate insulator as described in detail above and in connection withFIGS. 2-7C. A floating gate driver transistors, 901-1, 901-2, . . . ,901-N programmed in an off state remains in that state until the chargeis removed from its vertical floating gate.

Floating gate driver transistors, 901-1, 901-2, . . . , 901-N not havinga corresponding vertical floating gate charged operate in either an onstate or an off state, wherein input signals received by the input lines912A, 912B and 912C determine the applicable state. If any of the inputlines 912A, 912B and 912C are turned on by input signals received by theinput lines 912A, 912B and 912C, then a ground is provided to loaddevice transistors 916. The load device transistors 916 are attached tothe interconnect lines 914. The load device transistors 916 provide alow voltage level when any one of the floating gate driver transistors,901-1, 901-2, . . . , 901-N connected to the corresponding interconnectline 914 is activated. This performs the NOR logic circuit function, aninversion of the OR circuit function results from inversion of data ontothe interconnect lines 914 through the floating gate driver transistors,901-1, 901-2, . . . , 901-N of the array 900. When the floating gatedriver transistors, 901-1, 901-2, . . . , 901-N are in an off state, anopen is provided to the drain of the load device transistors 916. TheVDD voltage level is applied to corresponding input lines, e.g. theinterconnect lines 914 for second logic plane 922 when a load devicetransistors 916 is turned on by a clock signal received at the gate ofthe load device transistors 916 (Φ). Each of the floating gate drivertransistors, 901-1, 901-2, . . . , 901-N described herein are formedaccording to the teachings of the present invention as described indetail in connection with FIGS. 2-7C.

In a similar manner, second logic plane 922 comprises a second array offloating gate driver transistors, 902-1, 902-2, . . . , 902-N that areselectively programmed to provide the second level of the two levellogic needed to implement a specific logical function. In thisembodiment, the array of floating gate driver transistors, 902-1, 902-2,. . . , 902-N is also configured such that the output lines 920 comprisea logical NOR function of the signals from the interconnection lines 914that are coupled to particular output lines 920 through the floatinggate driver transistors, 902-1, 902-2, . . . , 902-N of the second logicplane 922.

Programmability of the vertical floating gate driver transistors, 902-1,902-2, . . . , 902-N is achieved by charging the vertical floating gate.When the vertical floating gate is charged, that floating gate drivertransistor, 902-1, 902-2, . . . , 902-N will remain in an off stateuntil it is reprogrammed. Applying and removing a charge to the verticalfloating gates is performed by tunneling charge between the floatinggate and control gates of the floating gate driver transistors, 901-1,901-2, . . . , 901-N through a low tunnel barrier interpoly, orintergate insulator as described in detail above and in connection withFIGS. 2-7C. A floating gate driver transistors, 902-1, 902-2, . . . ,902-N programmed in an off state remains in that state until the chargeis removed from the vertical floating gate.

Floating gate driver transistors, 902-1, 902-2, . . . , 902-N not havinga corresponding vertical floating gate charged operate in either an onstate or an off state, wherein signals received by the interconnectlines 914 determine the applicable state. If any of the interconnectlines 914 are turned on, then a ground is provided to load devicetransistors 924 by applying a ground potential to the source line orconductive source plane coupled to the transistors first source/drainregion as described herein. The load device transistors 924 are attachedto the output lines 920. The load device transistors 924 provide a lowvoltage level when any one of the floating gate driver transistors,902-1, 902-2, . . . , 902-N connected to the corresponding output lineis activated. This performs the NOR logic circuit function, an inversionof the OR circuit function results from inversion of data onto theoutput lines 920 through the floating gate driver transistors, 902-1,902-2, . . . , 902-N of the array 900. When the floating gate drivertransistors, 902-1, 902-2, . . . , 902-N are in an off state, an open isprovided to the drain of the load device transistors 924. The VDDvoltage level is applied to corresponding output lines 920 for secondlogic plane 922 when a load device transistor 924 is turned on by aclock signal received at the gate of the load device transistors 924(Φ). In this manner a NOR-NOR electrically programmable logic array ismost easily implemented utilizing the normal PLA array structure. Eachof the floating gate driver transistors, 902-1, 902-2, . . . , 902-Ndescribed herein are formed according to the teachings of the presentinvention as described in detail in connection with FIGS. 2-7C.

Thus FIG. 9 shows the application of the novel, non-volatile floatinggate transistors with low tunnel barrier intergate insulators in a logicarray. If a floating gate driver transistors, 901-1, 901-2, . . . ,901-N, and 902-1, 902-2, . . . , 902-N, is programmed with a negativecharge on the vertical floating gate it is effectively removed from thearray. In this manner the array logic functions can be programmed evenwhen the circuit is in the final circuit or in the field and being usedin a system.

The absence or presence of stored charge on the floating gates is readby addressing the input lines 912 or control gate lines andy-column/sourcelines to form a coincidence in address at a particularfloating gate. The control gate line would for instance be drivenpositive at some voltage of 1.0 Volts and the y-column/sourcelinegrounded, if the floating gate is not charged with electrons then thetransistor would turn on tending to hold the interconnect line on thatparticular row down indicating the presence of a stored “one” in thecell. If this particular floating gate is charged with stored electrons,the transistor will not turn on and the presence of a stored “zero”indicated in the cell. In this manner, data stored on a particularfloating gate can be read.

Programming can be achieved by hot electron injection. In this case, theinterconnect lines, coupled to the second source/drain region for thenon-volatile memory cells in the first logic plane, are driven with ahigher drain voltage like 2 Volts for 0.1 micron technology and thecontrol gate line is addressed by some nominal voltage in the range oftwice this value. Electrons can also be transfered between the floatinggate and the control gate through the low tunnel barrier intergateinsulator to selectively program the non-volatile memory cells,according to the teachings of the present invention, by the addressscheme as described above in connection with FIGS. 6A-6C. Erasure isaccomplished by driving the control gate line with a large positivevoltage and the sourceline and/or backgate or substrate/well addressline of the transistor with a negative bias so the total voltagedifference is in the order of 3 Volts causing electrons to tunnel off ofthe floating gates to the control gates. Writing can be performed, asalso described above, by either normal channel hot electron injection,or according to the teachings of the present invention, by driving thecontrol gate line with a large negative voltage and the the sourcelineand/or backgate or substrate/well address line of the transistor with apositive bias so the total voltage difference is in the order of 3 Voltscausing electrons to tunnel off of the control gates to the floatinggates. According one embodiment of the present invention, data can beerased in “bit pairs” since both floating gates on each side of acontrol gate can be erased at the same time. This architecture isamenable to block address schemes where sections of the array are erasedand reset at the same time.

One of ordinary skill in the art will appreciate upon reading thisdisclosure that a number of different configurations for the spatialrelationship, or orientation of the input lines 912, interconnect lines914, and output lines 920 are possible. That is, the spatialrelationship, or orientation of the input lines 912, interconnect lines914, and output lines 920 can parallel the spatial relationship, ororientation configurations detailed above for the floating gates andcontrol gates as described in connection with FIGS. 5A-5E

FIG. 10 is a simplified block diagram of a high-level organization of anelectronic system 1000 according to the teachings of the presentinvention. As shown in FIG. 10, the electronic system 1000 is a systemwhose functional elements consist of an arithmetic/logic unit (ALU),e.g. processor 1020, a control unit 1030, a memory unit 1040, or memorydevice 1040, and an input/output (I/O) device 1050. Generally such anelectronic system 1000 will have a native set of instructions thatspecify operations to be performed on data by the ALU 1020 and otherinteractions between the ALU 1020, the memory device 1040 and the I/Odevices 1050. The memory devices 1040 contain the data plus a storedlist of instructions.

The control unit 1030 coordinates all operations of the ALU 1020, thememory device 1040 and the I/O devices 1050 by continuously cyclingthrough a set of operations that cause instructions to be fetched fromthe memory device 1040 and executed. In service programmable logicarrays, according to the teachings of the present invention, can beimplemented to perform many of the logic functions performed by thesecomponents. With respect to the ALU 1020, the control unit 1030 and theI/O devices 1050, arbitrary logic functions may be realized in the“sum-of-products” form that is well known to one skilled in the art. Alogic function sum-of-products may be implemented using any of theequivalent two-level logic configurations: AND-OR, NAND-NAND, NOR-OR,OR-NOR, AND-NOR, NAND-AND or OR-AND, and using the novel non-volatilememory cells of the present invention.

CONCLUSION

The above structures and fabrication methods have been described, by wayof example and not by way of limitation, with respect to in serviceprogrammable logic arrays using non-volatile memory cells with lowtunnel barrier interpoly insulators.

It has been shown that the low tunnel barrier interpoly insulators ofthe present invention avoid the large barriers to electron tunneling orhot electron injection presented by the silicon oxide-silicon interface,3.2 eV, which result in slow write and erase speeds even at very highelectric fields. The present invention also avoids the combination ofvery high electric fields and damage by hot electron collisions in thewhich oxide result in a number of operational problems like soft eraseerror, reliability problems of premature oxide breakdown and a limitednumber of cycles of write and erase. Further, the low tunnel barrierinterploy dielectric insulator erase approach, of the present inventionremedies the above mentioned problems of having a rough top surface onthe polysilicon floating gate which results in, poor quality interpolyoxides, sharp points, localized high electric fields, prematurebreakdown and reliability problems.

According to the teachings of the present invention, any arbitrarycombinational logic function can be realized in the so-calledsum-of-products form. A sum of products may be implemented by using atwo level logic configuration such as the NOR-NOR arrays shown in FIG.10, or by a combination of NOR gates and NAND gates. A NAND gate can berealized by a NOR gate with the inputs inverted. By programming thefloating gates of the non-volatile memory cells in the array, thesearrays can be field programmed or erased and re-programmed to accomplishthe required logic functions.

DOCUMENTS

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1. A method for forming a programmable logic array, comprising: forminga first logic plane that receives a number of input signals, whereinforming the first logic plane includes forming a number of logic cellsarranged in rows and columns that are interconnected to provide a numberof logical outputs; forming a second logic plane, wherein forming thesecond logic plane includes forming a number of logic cells arranged inrows and columns that receive the outputs of the first logic plane andthat are interconnected to produce a number of logical outputs such thatthe programmable logic array implements a logical function; and whereinforming each of the logic cells includes; forming a first source/drainregion and a second source/drain region separated by a channel region ina substrate; forming a polysilicon floating gate opposing the channelregion and separated therefrom by a gate oxide, the floating gate havinga metal layer: forming a control gate opposing the floating gate; andforming a low tunnel barrier intergate insulator to separate the controlgate from the floating gate, the low tunnel barrier intergate insulatorin contact with the metal layer of the floating gate.
 2. The method ofclaim 1, wherein forming the low tunnel barrier intergate insulatorincludes forming a metal oxide insulator selected from the groupconsisting of lead oxide (PbO) and aluminum oxide (Al₂O₃).
 3. The methodof claim 1, wherein forming the low tunnel barrier intergate insulatorincludes forming a transition metal oxide insulator.
 4. The method ofclaim 3, wherein forming the transition metal oxide insulator includesforming the transition metal oxide insulator selected from the groupconsisting of Ta₂O₅, TiO₂, ZrO₂, and Nb₂O₅.
 5. The method of claim 1,wherein forming the control gate includes a forming a polysiliconcontrol gate having a metal layer formed thereon in contact with the lowtunnel barrier intergate insulator.
 6. The method of claim 1, whereinforming the first logic plane and the second logic plane each compriseforming NOR planes.
 7. A method for forming an in service programmablelogic array, comprising: forming a plurality of input lines forreceiving an input signal; forming a plurality of output lines; andforming one or more arrays having a first logic plane and a second logicplane connected between the input lines and the output lines, whereinforming the first logic plane and the second logic plane forming aplurality of logic cells arranged in rows and columns for providing asum-of-products term on the output lines responsive to the receivedinput signal, wherein forming each logic cell includes forming avertical non-volatile memory cell including: forming a vertical pillarextending outwardly from a semiconductor substrate at intersections ofthe input lines and interconnect lines and at the intersections of theinterconnect lines and the output lines, wherein each pillar includes afirst source/drain region, a body region, and a second source/drainregion; forming a number of floating gates opposing the body regions inthe number of pillars and separated therefrom by a gate oxide; forming anumber of polysilicon control gates opposing the floating gates, thecontrol gates having a metal layer; forming a low tunnel barrierintergate insulator to separate the control gate from the floating gate,the low tunnel barrier intergate insulator in contact with metal layerof the control gate; and forming a number of buried source lines formedof single crystalline semiconductor material and disposed below thepillars in the array for interconnecting with the first source/drainregions of column adjacent pillars in the array.
 8. The electronicsystem of claim 7, wherein forming the low tunnel barrier intergateinsulator includes forming a metal oxide insulator selected from thegroup consisting of PbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, and Nb₂O₅.
 9. Theelectronic system of claim 7, wherein forming each floating gateincludes forming a polysilicon floating gate having a metal layer formedthereon in contact with the low tunnel barrier intergate insulator. 10.The electronic system of claim 7, wherein forming each floating gateincludes forming a vertical floating gate formed in a trench below a topsurface of each pillar such that each trench houses a pair of floatinggates opposing the body regions in adjacent pillars on opposing sides ofthe trench.
 11. The electronic system of claim 10, wherein forming thenumber of control gates includes forming the control gates in the trenchbelow the top surface of the pillar and between the pair of floatinggates, wherein each pair of floating gates shares a single control gateline, and wherein each floating gate includes a vertically orientedfloating gate having a vertical length of less than 100 nanometers. 12.The electronic system of claim 10, wherein forming the number of controlgates includes forming the control gates in the trench below the topsurface of the pillar and between the pair of floating gates such thateach trench houses a pair of control gates each addressing the floatinggates one on opposing sides of the trench respectively, and wherein thepair of control gates are separated by an insulator layer.
 13. Theelectronic system of claim 10, wherein forming the number of controlgates includes forming the control gates disposed vertically above thefloating gates, and wherein each pair of floating gates shares a singlecontrol gate.
 14. The electronic system of claim 10, wherein forming thenumber of control gates includes forming the control gates disposedvertically above the floating gates, and wherein each one of the pair offloating gates is addressed by an independent one of the number ofcontrol gates.
 15. The electronic system of claim 7, wherein formingeach floating gate includes forming a horizontally oriented floatinggate formed in a trench below a top surface of each pillar such thateach trench houses a floating gate opposing the body regions in adjacentpillars on opposing sides of the trench, and wherein each horizontallyoriented floating gate has a vertical length of less than 100 nanometersopposing the body region of the pillars.
 16. The electronic system ofclaim 15, wherein forming the number of control gates includes formingthe control gates disposed vertically above the floating gates.
 17. Amethod for operating an in-server programmable logic array, comprising:writing to one or more floating gates of a number of non-volatile memorycells in one or more arrays using channel hot electron injection, theone or more arrays having a first logic plane and a second logic planeconnected between a number of input lines and a number of output lines,wherein number of non-volatile memory cells in the first logic plane andthe second logic plane are arranged in rows and columns for providing asum-of-products term on the output lines responsive to the receivedinput signal on the input lines, wherein each non-volatile memory cellincludes: a first source/drain region and a second source/drain regionseparated by a channel region in a substrate; a floating gate opposingthe channel region and separated therefrom by a gate oxide; a controlgate opposing the floating gate; and wherein the control gate isseparated from the floating gate by a low tunnel barrier intergateinsulator; erasing charge from one or more floating gates by tunnelingelectrons off of the floating gate and onto the control gate.
 18. Themethod of claim 17, wherein erasing charge from one or more floatinggates by tunneling electrons off of the floating gates and onto thecontrol gates further includes: providing a negative voltage to thesubstrate of an addressed cell; and providing a large positive voltageto the control gate of the addressed cell.
 19. The method of claim 17,wherein the method further includes writing to one or more floatinggates by tunneling electrons from the control gate to the floating gatein one or more addressed cells.
 20. The method of claim 19, whereinwriting to one or more floating gates by tunneling electrons from thecontrol gate to the floating gate in one or more addressed cells furtherincludes: applying a positive voltage to the substrate of an addressedcell; and applying a large negative voltage to the control gate of theaddressed cell.
 21. The method of claim 17, wherein erasing charge fromthe floating gate by tunneling electrons off of the floating gate andonto the control gate includes tunneling electrons from the floatinggate to the control gate through a low tunnel barrier intergateinsulator.
 22. The method of claim 21, wherein tunneling electrons fromthe floating gate to the control gate through a low tunnel barrierintergate insulator includes tunneling electrons from the floating gateto the control gate through a low tunnel barrier intergate insulatorselected from the group consisting of PbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, andNb₂O₅.
 23. The method of claim 21, wherein tunneling electrons from thefloating gate to the control gate through a low tunnel barrier intergateinsulator includes tunneling electrons from a metal layer formed on thefloating gate in contact with the low tunnel barrier intergate insulatorto a metal layer formed on the control gate and also in contact with thelow tunnel barrier intergate insulator.
 24. A method for operating anin-server programmable logic array, comprising: writing to one or morefloating gates of a number of non-volatile memory cells in one or morearrays using channel hot electron injection, the one or more arrayshaving a first logic plane and a second logic plane connected between anumber of input lines and a number of output lines, wherein number ofnon-volatile memory cells in the first logic plane and the second logicplane are arranged in rows and columns for providing a sum-of-productsterm on the output lines responsive to the received input signal on theinput lines, wherein each non-volatile memory cell includes: a number ofpillars extending outwardly from a substrate, wherein each pillarincludes a first source/drain region, a body region, and a secondsource/drain region; a number of floating gates opposing the bodyregions in the number of pillars and separated therefrom by a gateoxide; a number of control gates opposing the floating gates; a numberof buried sourcelines disposed below the number of pillars and coupledto the first source/drain regions along a first selected direction inthe array of non-volatile memory cells; a number of control gate linesformed integrally with the number of control gates along a secondselected direction in the array of non-volatile memory cells, whereinthe number of control gates lines are separated from the floating gatesby a low tunnel barrier intergate insulator; and a number of bitlinescoupled to the second source/drain regions along a third selecteddirection in the array of non-volatile memory cells; and erasing chargefrom the one or more floating gates by tunneling electrons off of theone or more floating gates and onto the number of control gates.
 25. Themethod of claim 24, wherein erasing charge from the one or more floatinggates by tunneling electrons off of the floating gate and onto thenumber of control gate further includes: providing a negative voltage toa substrate of one or more non-volatile memory cells; and providing alarge positive voltage to the control gate for the one or morenon-volatile memory cells.
 26. The method of claim 25, wherein themethod further includes erasing an entire row of non-volatile memorycells by providing a negative voltage to all of the substrates along anentire row of non-volatile memory cells and providing a large positivevoltage to all of the control gates along the entire row of non-volatilememory cells.
 27. The method of claim 25, wherein the method furtherincludes erasing an entire block of non-volatile memory cells byproviding a negative voltage to all of the substrates along multiplerows of non-volatile memory cells and providing a large positive voltageto all of the control gates along the multiple rows of non-volatilememory cells.
 28. A method for forming an in service programmable logicarray, comprising: forming a plurality of input lines for receiving aninput signal; forming a plurality of output lines; and forming one ormore arrays having a first logic plane and a second logic planeconnected between the input lines and the output lines, wherein formingthe first logic plane and the second logic plane forming a plurality oflogic cells arranged in rows and columns for providing a sum-of-productsterm on the output lines responsive to the received input signal,wherein forming each logic cell includes forming a vertical non-volatilememory cell including: forming a vertical pillar extending outwardlyfrom a semiconductor substrate at intersections of the input linesinterconnect lines and at the intersections of the interconnect linesand the output lines, wherein each pillar includes a first source/drainregion, a body region, and a second source/drain region; forming anumber of floating gates opposing the body regions in the number ofpillars and separated therefrom by a gate oxide; forming a number ofcontrol gates opposing the floating gates; forming a low tunnel barrierintergate insulator to separate the control gate from the floating gate,wherein forming the low tunnel barrier intergate insulator includesforming a metal oxide insulator selected from the group consisting ofPbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, and Nb₂O₅; and forming a number of buriedsource lines formed of single crystalline semiconductor material anddisposed below the pillars in the array for interconnecting with thefirst source/drain regions of column adjacent pillars in the array. 29.A method for forming an in service programmable logic array, comprising:forming a plurality of input lines for receiving an input signal;forming a plurality of output lines; and forming one or more arrayshaving a first logic plane and a second logic plane connected betweenthe input lines and the output lines, wherein forming the first logicplane and the second logic plane forming a plurality of logic cellsarranged in rows and columns for providing a sum-of-products term on theoutput lines responsive to the received input signal, wherein formingeach logic cell includes forming vertical non-volatile memory cellincluding: forming a vertical pillar extending outwardly from asemiconductor substrate at intersections of the input lines andinterconnect lines and at the intersections of the interconnect linesand the output lines, wherein each pillar includes a first source/drainregion, a body region, and a second source/drain region; forming anumber of floating gates opposing the body regions in the number ofpillars and separated other from by a gate oxide; forming a number ofcontrol gates opposing the floating gates, wherein forming each floatinggate includes forming a polysilicon floating gate having a metal layerformed thereon in contact with the low tunnel barrier intergateinsulator; forming a low tunnel barrier intergate insulator to separatethe control gate from the floating gate; and forming a number of buriedsource lines formed of single crystalline semiconductor material anddisposed below the pillars in the array for interconnecting with thefirst source/drain regions of column adjacent pillars in the array. 30.The electronic system of claim 29, wherein forming the low tunnelbarrier intergate insulator includes forming a metal oxide insulatorselected from the group consisting of PbO, Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, andNb₂O₅.
 31. A method for forming an in service programmable logic array,comprising: forming a plurality of input lines for receiving an inputsignal; forming a plurality of output lines; and forming one or morearrays having a first logic plane and a second logic plane connectedbetween the input lines and the output lines, wherein forming the firstlogic plane and the second logic plane forming a plurality of logiccells arranged in rows and columns for providing a sum-of-products termon the output lines responsive to the received input signal, whereinforming each logic cell includes forming vertical non-volatile memorycell including: forming a vertical pillar extending outwardly from asemiconductor substrate at intersections of the input lines andinterconnect lines and at the intersections of the interconnect linesand the output lines, wherein each pillar includes a first source/drainregion, a body region, and a second source/drain region; forming anumber of floating gates opposing the body regions in the number ofpillars and separated therefrom by a gate oxide, wherein forming eachfloating gate includes forming a vertical floating gate formed in atrench below a top surface of each pillar such that each trench houses apair of floating gates opposing the body regions in adjacent pillars onopposing sides of the trench; forming a number of control gates opposingthe floating gates, wherein forming each floating gate includes forminga polysilicon floating gate having a metal layer formed thereon incontact with the low tunnel barrier intergate insulator, wherein formingthe number of control gates includes forming the control gates disposedvertically above the floating gates, and wherein each one of the pair offloating gates is addressed by an independent one of the number ofcontrol gates; forming a low tunnel barrier intergate insulator toseparate the control gate from the floating gate; and forming a numberof buried source lines formed of single crystalline semiconductormaterial and disposed below the pillars in the array for interconnectingwith the first source/drain regions of column adjacent pillars in thearray.